The present invention relates to a semiconductor memory device with an improved yield.
In the manufacture of semiconductor memory devices, together with an increase in the memory capacity of the device, the probability of occurrence of error bits also increases. Semiconductor memory cells containing error bits have always been regarded as defective memory devices, and discarded as such. This discarding of defective memory devices results in an increase of manufacturing costs and a waste of material.
In recent years, to remedy such defects, some measures have been taken to save defective memory devices. One example of such a measure would be to provide an auxiliary memory in addition to a main memory, so that, when the main memory contains an error bit, the auxiliary memory is used in place of the error bit, thus saving the defective main memory. In other words, this example provides a redundancy function for the main memory containing the error bit by the provision of the auxiliary memory.
A schematic illustration of the semiconductor memory device with such an auxiliary memory is given in FIG. 1. In the figure, an output signal from an address buffer 1 is applied to a main address decoder 2 and an auxiliary address decoder 3. A decoded output of the main address decoder 2 is applied to a main memory 4, thereby selecting one of the row lines in the main memory. Then, data is written into or read out from the memory cells coupled with the row lines selected, by a write signal or a read signal. The main address decoder 2 is controlled in its decode operation by the output from the auxiliary address decoder 3. The decoded output in the auxiliary address decoder 3 is applied to the auxiliary memory 5 to select one of the row lines in the auxiliary memory 5. Then, data is written into the memory cell connected to the selected row line using a write signal and read out of the same by a read signal.
The auxiliary address decoder 3 is so programmed that when the main memory 4 contains an error bit cell, it produces the decoded output corresponding to the address of the error bit cell. Therefore, when an error bit cell in the main memory 4 is selected, the output of the auxiliary decoder 3 selects the auxiliary memory 5. In this specification, "an error bit cell is selected" means "a row line connected to an error bit cell is selected", for ease of explanation. Similarly, "an auxiliary memory 5 is selected" is used to mean "a row line connected to the memory cell of the auxiliary memory 5, which is used in place of the error bit cell in the main memory, is selected".
The auxiliary address decoder 3 operates under the control of an error bit replacement control signal generator 6 for generating a control signal for error bit replacement. The error bit replacement control signal generator 6, which includes nonvolatile memory elements, stores the information which, when an error bit is contained in the main memory 4, operates the auxiliary decoder so as to select the bit cell of the auxiliary memory 5 in place of the error bit cell. The control signal generator 6 outputs a control signal for the error bit replacement to the auxiliary address decoder 3 on the basis of the information, thereby controlling the operation.
In the semiconductor memory device thus arranged, when no error bit cell is present in the main memory 4, no control signal is produced and only the main memory operates to select a correct bit cell. The phrase "a correct bit cell is selected" means "a row line connected to a correct bit cell is selected". When the error bit cell is contained in the main memory, the auxiliary address decoder 3 selects a memory cell in the auxiliary memory 5. Further, at this time, the decoded output of the auxiliary address decoder 3 stops the decoding operation of the main address decoder 2, blocking access to the main memory 4. Through this operation, the error bit cell in the main memory 4 is replaced with a memory cell in the auxiliary memory 5.
FIGS. 2A and 2B show circuit diagrams of two examples of the error bit replacement control signal generator 6. In the example of FIG. 2A, a fuse element F made of polysilicon as a nonvolatile memory element is inserted between a power source VD and an output terminal Out. A programming enhancement-type MOS transistor 7 is inserted between the output terminal Out and ground. A depletion-type MOS transistor 8 is inserted between the output terminal Out and ground. A programming signal P is applied to the gate of the MOS transistor 7. The MOS transistor 8 is connected to ground. In the circuit shown in FIG. 2B, a programming enhancement-type MOS transistor 7 is inserted between a power source VD applying point and an output terminal Out. A depletion-type MOS transistor 8 is inserted between the VD applying point and the output terminal Out. A fuse F is connected between the output terminal Out and ground. A programming signal P is applied to the gate of the MOS transistor 7 and the gate of the MOS transistor 8 is coupled to the output terminal Out.
In the circuit shown in FIG. 2A, when the fuse F is not burned out, a signal level at the output terminal Out is kept at logical "1" since a resistance ratio of the MOS transistor 8 to the fuse element F is extremely large. On the other hand, when it is burned out, the output terminal Out is grounded through the MOS transistor 8 and kept at logical "0". To melt the fuse F, a programming signal P of logical "1" is applied to the gate of the MOS transistor 7. The application of the programming signal P turns on the MOS transistor 7 to allow a large current to flow through the fuse F. Joule heat generated at this time burns out the fuse F. When the fuse F is burned out, the signal P is again logical "0" to cut off the MOS transistor 7. When a signal at the output terminal Out, i.e., the error bit replacement control signal, is logical "1", for example, the decoding operation of the auxiliary address decoder 3 is stopped. When it is logical "0", for example, the decoding operation is performed.
In the circuit shown in FIG. 2B, unlike the circuit shown in FIG. 2A, when the fuse F is not burned out, a signal level at the output terminal Out is kept at logical "0" due to a resistance ratio of the MOS transistor 8 to the fuse F. When it is burned out, the output terminal Out is connected to the power source VD via the MOS transistor 8, and is at logical "1". To burn out the fuse F, a programming signal P of logical "1" is applied to the gate of the MOS transistor 7. Upon application of the programming signal P, the MOS transistor 7 turns on to allow a large current to flow through the fuse F. In this circuit, when the signal at the output terminal Out, or the control signal, is logical "0", the decoding operation of the auxiliary address decoder 3 is stopped; when it is logical "1", the decoding operation is performed.
FIG. 3 shows a configuration of the auxiliary address decoder 3 when no error bit replacement control signal generator 6 is used. The auxiliary address decoder comprises a depletion-type MOS transistor 9, a plurality of drive MOS transistors 10 of the enhancement type, having at their inputs address signals A0, A0, A1, A1, . . . An produced from the address buffer 1, and a plurality of fuses FB inserted between the MOS transistors 10 and 9.
The auxiliary decoder is so programmed that, of the memory cells of the memory 4, if a memory cell selected by the address signals A0=A1=. . .=An=0 is an error bit cell, it produces a decode output corresponding to the address. This programming is performed by burning out the fuse FB connected to the MOS transistor 10 receiving the address signals A0, A1, . . . An at the gate. When the auxiliary address decoder is so programmed, upon the inputting of the address signals A0=A1 =. . . =An=0, a memory cell is specified in the auxiliary memory.
In the auxiliary address decoder shown in FIG. 3, it is necessary to burn out the plurality of fuses FB determined by the contents of the address signal input for selecting the auxiliary memory. These fuse elements are melted by Joule heat from a laser or the current as mentioned above. However, this melting method involves some problems: sticking of melted material to the peripheral circuit, reduction of the reliability of the memory device, or erroneous programming due to a melting failure, or poor reliability of the melted portion. Therefore, in order to avoid these probelms it is evident that the number of melting portions should be as small as possible. With recent progress in discrete fabricating techniques for integrated circuits, the memory capacity has been increased and hence, the number of bits of an address input has also increased. Thus, the number of fuse elements burned out when the auxiliary memory is used increases. For this reason, an immediate solution to the above-mentioned problems has been eagerly desired.
FIG. 4 shows another embodiment of a prior auxiliary memory. This auxiliary decoder does not use the fuse elements FB used in the auxiliary decoder of FIG. 3 but uses programming circuits instead. The programming circuits are respectively provided for the drive transistors 10 in a one-to-one corresponding manner. For ease of illustration, only one programming circuit denoted as "11i" is illustrated. The drive transistor 10i is gate-controlled by a programming circuit Ci derived from the programming circuit 11i. The other drive transistors 10.sub.0 to 10.sub.m are gate-controlled by programming signals applied from the corresponding programming circuits. Also in this circuit, an enhancement-type MOS transistor 10.sub.DR is provided in parallel with the drive transistors 10.sub.0 to 10.sub.m. The programming circuit 10i is comprised of a fuse element FC, enhancement-type MOS transistors 12 to 17, and depletion-type MOS transistors 18 to 20. The drain-source paths of the MOS transistors 12 and 13 are coupled at one end with an address signals Ai and Ai, respectively. A control signal for error bit replacement generated and delivered from the control signal generator 6 (see FIG. 1) is input to the gates of the transistors 16 and 17. An output signal OUT derived from the error bit replacement control signal generator 6 is also applied to the gate of the parallel-connected transistor 10.sub.DR. The other ends of the MOS transistors 12 and 13 are connected together and the common connection point provides an output terminal connected to the gate of the drive transistor 10i.
With such an arrangement, when the auxiliary memory is not used, the replacement signal OUT is set at logical "1". In this case, the MOS transistor 10.sub.DR is turned on, and therefore the auxiliary memory is not selected.
When an error memory cell is present in the main memory and the auxiliary memory is used, the replacement signal OUT is logical "0". In this case, the MOS transistor 10.sub.DR is off, so that the output signal level of the auxiliary decoder is determined by the logic levels of the gate control signals C0, C1, . . . , Ci, . . . , Cm. If the cell at the address location specified by the address signal A0=0 is an error bit cell, the fuse element FC is melted. Then, the gate of the MOS transistor 12 becomes logical "1" and the MOS transistor 12 is turned on. The MOS transistor 13 is turned off and its gate is logical "038 . The programming circuit 11i produces the input address signal Ai as the output signal Ci. Accordingly, when the logical "0" signal comes in as the input address signal Ai, the programming signal Ci from the programming circuit 11i is logical "0" and the drive transistor 10i supplied with the programming signal Ci is off. Therefore, when all other drive transistors 10.sub.0 to 10.sub.m are off, the auxiliary memory is selected.
Let us consider a case where a memory bit cell at an address location specified by the address signal Ai=1 is an error bit cell. In this case, the fuse element FC is not burned out. Accordingly, the transistor 12 is off while the transistor 13 is on. The circuit 11i produces an input address signal Ai as a programming signal Ci. Accordingly, if the input address signal Ai is logical "1" (i.e., Ai=0), the output signal Ci produced from the circuit 11i is also logical "0", so that the drive transistor 10i is off. Accordingly, as in the previous case, when all of the other drive transistors 10.sub.0 to 10.sub.m are off, the auxiliary memory is selected. With this circuit construction, when an error bit cell is in address Ai=1 it is unnecessary to melt the fuse element FC. Therefore, the number of fuse elements FC to be melted becomes less in this circuit construction than in that of the FIG. 3 circuit.
As described above, in conventional semiconductor memory devices with a redundancy function as shown in FIGS. 1 to 4, current flows through the auxiliary memory and auxiliary address decoder even when they are not used, thus wasting power. When the auxiliary memory and the auxiliary address decoder are used, the corresponding main decoder circuit and main memory area are not used. In the above-mentioned semiconductor memory device, current also flows into the main decoder circuit and the main memory area, which are not being used, thus wasting more power.
By convention, in order to judge whether or not an error bit cell is present in the main memory, a memory bit cell in the main memory is selected by the main address decoder, and data is stored into the selected memory bit cell. Then, the data is read out and compared with the original data. In the case of a memory in which the power dissipation at the time of stand-by must be reduced to substantially zero, as in CMOSRAM's (complementary MOS transistors), even a memory cell where an extremely small current flows must be treated as an error bit cell. This extremely small current may be, for example, a leak current flowing through the transistor, a leak current due to detection of a PN junction, a short current in the memory bit cell when the power source and ground are shorted by an extremely large resistor element in the memory cell, or the like. These currents are extremely small, and do not lead to the destruction of data in the memory bit cell. Therefore, the conventional detecting method judges the memory bit cell with such an extremely small current as a correct memory cell. In other words, the conventional detecting method cannot detect memory cells with an extremely small current.